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To show how the use of conductor spacings below 4 mil in printed wiring boards (PWBs) can introduce an unanticipated failure mechanism, leading to current leakage and short circuit failure.

The tests in this study were conducted in accordance with IPC‐TM‐650 2.6.25, using boards designed with conductor spacings between plated through holes (PTHs) ranging from 6 to 3 mil and from 8 to 3 mil between PTHs and ground planes. The board types and conductor spacings were selected to include current and future printed circuit board fabrication technology.

For PWBs that may be used in harsh environments where the relative humidity and temperature may approach those of the test environments, even for relatively short periods of time, spacings of 4 mil or less in the materials tested may not be appropriate. However, it is unlikely that the 85°C and 85 percent RH conditions are the minimum conditions to induce this failure mechanism. More tests at lower temperatures and relative humidity combinations should be conducted to evaluate conditions at which this type of failure begins.

The value of the paper lies in that the tests show that the IPC industry standard for conductive filament formation (CFF) testing of PTH‐PTH conductor spacings of 4 mil or less, at 85°C/85 percent RH can introduce a CFF variant failure mechanism, and therefore, may need to be modified to ensure that the test conditions accelerate the CFF mechanism and not other low resistance paths.

Summarizes the flat panel display (FPD) industry outside of Japan, with a focus on advances in Korea and Taiwan. Discusses the major manufacturers in each country as well as their current status. Concludes with a brief discussion on the future outlook of the FPD market.

The reliability of hard disk drives (HDDs) is dependent on the drive construction, as well as the operational and environmental conditions, in which the drive is used. Self-monitoring, analysis and reporting technology (SMART) continuously provides attribute information on HDD usage and degradation characteristics.

This paper aims to analyze the reported failures Backblaze data set for ST3000DM001 HDDs intended for desktop applications within a data center application. SMART attributes used for predicting failure are discussed and analyzed over the life of many hard drives. A case study on the actual use of SMART and the limitations of the SMART attribute information, the data center’s information and the use of desktop drives in a commercial application are also presented.

The analysis showed that when Backblaze started to record the data, the hard disk drives had already worked for a while with power on hours mean and standard deviation of 6,683 and 365 h, respectively. Therefore, it is possible that some SMART attributes have experienced critical values that have not been recorded by Backblaze. Additionally, 8% of all ST3000DM001 drives that Backblaze labeled as failed did not have raw values above zero for the five attributes that were considered critical. Backblaze recorded 25 SMART attributes in total for all hard disk drive brands where ST3000DM001 having 83.3% of the attributes ranked as the drive with the most attributes recorded. Having more recorded attributes with critical values leads to label more ST3000DM001 drives as failed while there might be the hard drives from the other brands or part numbers that experienced more critical SMART attributes but were not labeled as failed because of the lack of records.

It is an original work carried out at the Center for Advanced Life Cycle Engineering, University of Maryland.

The paper presents an alternative solution to address part obsolescence. This paper discusses approaches to solve part obsolescence including an uprating approach. This paper also describes the methods to uprate parts, and demonstrates the practical application of the uprating approach in the form of a case study.

This paper has been written to provide an understanding of the uprating approach to mitigate the problems caused by part obsolescence. The paper discusses the challenge faced due to part obsolescence, the temperature ratings for electronic parts, the uprating methods and finally explains the use of uprating to mitigate part obsolescence in the form of a case study. The part being uprated is a microcontroller unit used in many avionics applications. The case study describes a particular use of uprating and the return on investment.

Based on the uprating approach, it was discovered that for the particular application, the commercially available plastic quad flat pack microcontroller could be used as a substitute for the “military” ceramic BGA version, which was discontinued by the manufacturer. It was discovered that there would be no problem with the commercial part's quality or reliability for the particular application. Parametric tests showed no evidence of instability of electrical characteristics over the uprated temperature range. There was substantial return on investment due to the use of uprated parts.

This paper can help electronics manufactures deal with part obsolescence. This paper demonstrates the practicality of uprating parts. Uprating can save companies money by reducing the need for life‐time buys, substitution of parts and even redesign.

The paper provides an alternative approach to address the problem of part obsolescence. This paper shows that proper uprating leads to cost saving while continuing to provide reliable service.

Non‐woven laminates have begun to gain recognition in the electronics industry because they are generally thinner and flatter than woven laminates. This study characterizes the mechanical and thermo‐mechanical properties of non‐woven, randomly dispersed, short fiber laminates, and identifies potential failure mechanisms which must be addressed in the design and utilization of printed circuit boards using non‐woven technology.

Life cycle cost (LCC) analysis is one of the key parameters in designing a sustainable product or system. The application of life cycle costing in the manufacturing industries is still limited due to several factors. Lack of understanding of LCC analysis methodologies is one of the key barriers. This paper presents a generalized framework for LCC analysis of repairable systems using reliability and maintainability principles.

The developed LCC analysis framework and stochastic point processes are applied for the analysis of a typical computerized numerical control turning center (CNCTC) and governing equations for acquisition cost, operation cost, failure cost, support cost and net salvage value are developed. The LCC of the CNCTC is evaluated for the renewal process (RP) and minimal repair process (MRP) approach.

The LCC analysis of the CNCTC reveals that, the acquisition cost is only 7.59% of the LCC, whereas the operation, failure and support costs dominate and contribute nearly 93% of the LCC. The LCC per day for RP requires additional US$ 1.03 than that for MRP. The detailed LCC analysis of the CNCTC identifies the critical components of CNCTC and these components are: spindle motor, spindle motor cooling fan, spindle belt, drawbar, spindle bearing, oil seals, hydraulic hose, solenoid valve, tool holder, lubrication pump motor system, lubrication hose, coolant pump motor system, coolant hose, supply cables, drive battery.

The developed framework of LCC of a repairable system can be applied to any other repairable systems with the appropriate modifications. LCC analysis of CNCTC reveals that the procurement decision of a product or system should be based on LCC and not only on the acquisition cost. The optimum utilization of consumables such as cutting tools, coolant, oil and lubricant can save operation cost. Thus, use of high-efficiency electric motors and the usage of recommended consumables can prolong the life of several components of a system. Therefore, due consideration and attention to these parameters at product design stage itself will decrease failure and support cost and ultimately its LCC.

The purpose of this paper is to present an analytical approach to find the reduction in the required number of surface mount capacitors by the use of embedded capacitors in decoupling applications.

The analytical model used to perform decoupling is cavity model from theory of microstrip antenna and N‐port impedance matrix. The methodology involves addition of decoupling capacitors between the power and the ground plane such that the impedance between ports on the power‐ground plane becomes lower than the target impedance at that frequency. A case study is presented in which a 0.3 m×0.3 m power‐ground plane is decoupled by using various combinations of surface mount capacitors and embedded capacitors in the frequency range of 0.001‐1 GHz and at a target impedance of 0.1, 0.01, and 0.001 Ω. The total number of surface mount capacitors are compared in each case.

Use of embedded planar capacitors with a thin dielectric (about 8 mm) dampened board resonances at high frequency, as compared to a thick dielectric. Embedded capacitors are found to reduce the number of surface mount capacitors when the target impedance is low and the operating frequency is high.

The methodology discusses in this paper is applicable to a simplified power‐ground plane (which has no cut‐outs and is rectangular in shape) as compared to actual digital circuits.

This methodology can be used as a quick preliminary tool to evaluate the decrease in the number of surface mount capacitors (by the use of embedded capacitors) as compared to complex and time consuming electromagnetic solvers.

This paper seeks to introduce a set of key practices that can be used to assess whether an organization has the ability to design, develop and manufacture reliable electronic products.

The ability to design, develop and manufacture reliable electronic products is defined in the paper in terms of a reliability capability maturity model, which is a measure of the practices within an organization that contribute to the reliability of the final product, and the effectiveness of these practices in meeting the reliability requirements of customers.

The paper presents a procedure for evaluating and benchmarking reliability capability. Criteria for assigning different capability maturity levels are presented. The paper also presents a case study corresponding to reliability capability benchmarking of an electronics company.

The paper provides a set of practices for evaluating and benchmarking reliability capability.

The purpose of this paper is to present the results from work on a project aimed at evaluating six different copper alloy substrates coated with pure tin for tin whisker growth. The influence of intermetallic growth between the copper alloy substrate and the tin‐plating on the growth of tin whiskers has been investigated.

The experiment consisted of six substrates of different alloys of copper, plated with bright tin including copper beryllium, cartridge brass, phosphor bronze, Cu‐Ni‐Si “7025” and Cu‐Ni‐Sn “spinodal”. The samples were mechanically stressed and then subjected to temperature humidity storage conditions for 1,000 h. These samples were then evaluated for tin whisker growth and intermetallic layer thickness.

Of the six samples five showed tin whisker growth. For these samples the intermetallic layer thickness has little effect on tin whisker growth. Sample with Cu‐Ni‐Sn “spinodal” alloy substrate showed very low whisker density and comparatively lower maximum whisker length than the other tested substrate material.

More samples per condition should be evaluated to bolster the conclusions. For the sample without tin whisker growth, holes on the surface of the plating were observed. The holes in the plating provide an opportunity for stress relaxation after the plating process. Since stress in the plating layer is low, tin whiskers are not formed on the sample surface.

The paper details the tin whisker growth on six tin plated copper substrate samples. The intermetallic layer thickness for each copper alloy substrate is calculated. The relationship between the intermetallic layer thickness and tin whisker growth for the six substrates are discussed.

This paper seeks to present a prognostics approach using the Mahalanobis distance (MD) method to predict the reliability of multilayer ceramic capacitors (MLCCs) in temperature‐humidity‐bias (THB) conditions.

Data collected during THB testing of 96 MLCCs were analyzed using the MD method. In the THB tests, three parameters (capacitance (C), dissipation factor (DF), and insulation resistance (IR)) were monitored in situ. A Mahalanobis space (MS) was formed from the MD values of a set of non‐failed MLCCs. MD values for the remaining MLCCs were compared with an MD threshold. Data for MLCCs which exceeded the threshold were examined using the failure criteria for the individual electrical parameters to identify failures and precursors to failure.

It was found that the MD method provided an ability to detect failures of the capacitors and identify precursors to failure, although the detection rate was not perfect.

It was observed that the quality and construction of the MS, together with the choice of the MD threshold, were the critical factors determining the sensitivity of the MD method. Recommendations are offered for improved sensitivity to enable assessment of intermittent failures.

MD analysis of the multivariate MLCC data set illustrates how detection of failures can be simplified in a system for which several parameters were monitored simultaneously. This makes the MD method of great potential value in a health‐monitoring system.